Instruction Level Parallelism - a historical perspective: Prof. Roland Ibbett, EPCC (70 mins, ~64 MB)

EPCC Guest Lectures

Контент предоставлен Iain Bethune and Iain Bethune (ibethune@exseed.ed.ac.uk). Весь контент подкастов, включая эпизоды, графику и описания подкастов, загружается и предоставляется непосредственно компанией Iain Bethune and Iain Bethune (ibethune@exseed.ed.ac.uk) или ее партнером по платформе подкастов. Если вы считаете, что кто-то использует вашу работу, защищенную авторским правом, без вашего разрешения, вы можете выполнить процедуру, описанную здесь https://ru.player.fm/legal.

15y ago 1:10:00

MP3•Главная эпизода

This talk traces the development of the different types of instruction-level parallelism that have been incorporated into the hardware of processors from the early 1960s to the present day. We will see how the use of parallel function units in the CDC 6600 eventually led to the design of the Cray-1 with its vector processing instructions and superscalar processors such as the Alpha. The talk also covers Very Long Instruction Word systems and SIMD systems. The talk is accompanied by visual demonstrations of the activities that occur within processors using simulation models developed using the HASE computer architecture simulation environment.
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Slides - Talk slides

19 эпизодов

#Higher Education #Podcasting Education #Iain Bethune #Iain Bethune (ibethune@exseed.ed.ac.uk #EPCC #University Of Edinburgh